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PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION 1 Z86E02 SL1925 CMOS Z8 OTP MICROCONTROLLER (R) 1 FEATURES Part Number Z86E02 * General-Purpose s s ROM (Kilobytes) 0.5 RAM* (Bytes) 61 Speed (MHz) 8 s 18-Pin DIP and SOIC Packages 3.5V to 5.5V Operating Range @ 0C to +70C 4.5V to 5.5V Operating Range @ -40C to +105C 14 Input / Output Lines Five Vectored, Prioritized Interrupts with Programmable Polarity Two Analog Comparators WDT/Power-On Reset (POR) s Program Options: - Low Noise - ROM Protect - Auto Latch - Permanent Watch-Dog Timer (WDT) - EPROM/TEST Mode Disable - RC Oscillator One Programmable 8-Bit Counter/Timer, with 6-Bit Programmable Prescaler On-Chip Oscillator that Accepts RC, XTAL, Ceramic Resonance, LC, or External Clock Clock-Free WDT Reset Low-Power Consumption (50 mw) Fast Instruction Pointer (1.5 s @ 8 MHz) s s s s s s s s GENERAL DESCRIPTION Zilog's Z86E02 Microcontroller (MCU) is a One-Time Programmable (OTP) member of the Z8 single-chip microcontroller family which allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions. For applications demanding powerful I/O capabilities, the Z86E02's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O. An on-chip counter/timer, with a large number of user selectable modes, offload the system of administering realtime tasks such as counting/timing and I/O data communications. Note: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC Device VDD VSS GND CP97DZ83501 PRELIMINARY 1 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog GENERAL DESCRIPTION (Continued) Input Vcc GND XTAL Port 3 Machine Timing & Inst. Control Counter/ Timer ALU Interrupt Control FLAG OTP Two Analog Comparators Register Pointer General-Purpose Register File Program Counter Port 2 Port 0 I/O (Bit Programmable) I/O Figure 1. Functional Block Diagram 2 PRELIMINARY CP97DZ83501 Zilog Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller D7-D0 Address MUX Z8 MCU A10-A0 1 Data MUX Z8 PORT2 D7-D0 /OE P31 A10-A0 0.5K EPROM D7-D0 ROM PROT Low Noise Address Counter A10-A0 3 Bits PGM Mode Logic Clear Clock P00 P01 EPM /CE /PGM P32 XT1 P02 VPP P33 Figure 2. EPROM Programming Mode Block Diagram CP97DZ83501 PRELIMINARY 3 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog PIN DESCRIPTION D4 D5 D6 D7 VCC N/C /CE /OE EPM 1 18 DIP 18 - Pin 9 10 D3 D2 D1 D0 GND /PGM CLOCK CLEAR VPP P24 P25 P26 P27 VCC XTAL2 XTAL1 P31 P32 1 18 DIP 18 - Pin 9 10 P23 P22 P21 P20 GND P02 P01 P00 P33 Figure 3. 18-Pin EPROM Mode Configuration Table 1. 18-Pin DIP Pin Identification EPROM Programming Mode Pin # Symbol Function 1-4 5 6 7 8 9 10 11 12 13 14 15-18 D4-D7 VCC N/C /CE /OE EPM VPP Clear Clock /PGM GND D3-D0 Data 4, 5, 6, 7 Power Supply No Connection Chip Enable Output Enable EPROM Prog Mode Prog Voltage Clear Clock Address Prog Mode Ground Data 0,1, 2, 3 Figure 4. 18-Pin DIP/SOIC Standard Mode Configuration Table 2. 18-Pin DIP/SOIC Pin Identification Direction In/Output Standard Mode Pin # Symbol 1-4 5 P24-P27 Vcc XTAL2 XTAL1 P31 P32 P33 P00-P02 GND P20-P23 Function Port 2, Pins 4,5,6,7 Power Supply Crystal Osc. Clock Crystal Osc. Clock Port 3, Pin 1, AN1 Port 3, Pin 2, AN2 Port 3, Pin 3, REF Port 0, Pins 0,1,2 Ground Port 2, Pins 0,1,2,3 Direction In/Output Output Input Input Input Input In/Output In/Output Input Input Input Input Input Input Input In/Output 6 7 8 9 10 11-13 14 15-18 4 PRELIMINARY CP97DZ83501 Zilog Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS Voltage on VDD Pin with Respect to VSS Voltage on Pins 7, 8, 9, 10 with Respect to VSS Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin Maximum Allowable Current into an Open-Drain Pin Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin -600 -600 dissipation should not exceed 462 mW for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [I DD - (sum of IOH)] + sum of [(V DD - VOH) x IOH] + sum of (V0L x I0L) Min -40 -65 -0.7 -0.3 -0.6 Max +105 +150 +12 +7 VDD+1 462 240 240 +600 +600 20 20 Units C C V V V mW mA mA A A mA mA 3 4 2 Note 1 1 Notes: [1] This applies to all pins except where otherwise noted. Maximum current into pin must be 600 A. [2] There is no input protection diode from pin to V (not applicable to EPROM Mode). [3] This excludes Pin 6 and Pin 7. [4] Device pin is not at an output Low state. DD STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 5). From Output Under Test 150 pF Figure 5. Test Load Diagram CP97DZ83501 PRELIMINARY 5 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 10 pF 20 pF 25 pF DC ELECTRICAL CHARACTERISTICS TA = 0C to +70C Sym Vinmax VCH Parameter Max Input Voltage Clock Input High Voltage VCC [4] 3.5V 5.5V 3.5V 5.5V VCL Clock Input Low Voltage 3.5V 5.5V VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V VOL1 Output Low Voltage 3.5V 5.5V 3.5V 5.5V VOL2 Output Low Voltage 3.5V 5.5V VOFFSET Comparator Input Offset Voltage VLV IIL VCC Low Voltage Protection Input Leakage (Input Bias Current of Comparator) 3.5V 5.5V 2.6 3.5V 5.5V -1.0 -1.0 0.8 VCC 0.8 VCC VSS-0.3 VSS-0.3 0.7 VCC 0.7 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 0.8 0.4 0.4 0.4 1.2 1.2 25.0 25.0 3.2 1.0 1.0 Min Max 12 12 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC 1.7 2.8 0.8 1.7 1.8 2.8 0.8 1.5 3.0 4.8 3.0 4.8 0.2 0.1 0.2 0.1 1.0 0.8 10.0 10.0 2.9 Typical Note 4 @ 25C Units Conditions V V V V V V V V V V V V V V V V V V V V mV mV V A A IOH = -2.0 mA IOH = -2.0 mA Low Noise @ IOH = -0.5 mA Low Noise @ IOH = -0.5 mA IOL = +4.0 mA IOL = +4.0 mA Low Noise @ IOL = 1.0 mA Low Noise @ IOL = 1.0 mA IOL = +10 mA, IOL = +10 mA, 5 5 5 5 5 5 IIn<250 A IIn<250A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Notes 1 1 @ 4 MHz Max. Int. CLK Freq. VIN = 0V, VCC VIN = 0V, VCC 6 PRELIMINARY CP97DZ83501 Zilog Typical Note 4 @ 25C Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller TA = 0C to +70C Sym IOL VVICR Parameter Output Leakage Comparator Input Common Mode Voltage Range Supply Current VCC [4] 3.5V 5.5V Min -1.0 -1.0 Max 1.0 1.0 Units Conditions A A V VIN = 0V, VCC VIN = 0V, VCC Notes 1 VSS-0.3 VCC -1.0 ICC 3.5V 5.5V 3.5V 5.5V 3.5 7.0 8.0 11.0 2.5 4.0 4.0 5.0 3.5 7.0 5.8 9.0 8.0 11.0 1.5 6.8 3.0 8.2 0.7 2.5 1.0 3.0 1.5 6.8 2.5 7.5 3.0 8.2 mA mA mA mA mA mA mA mA mA mA mA mA mA mA ICC1 Standby Current 3.5V 5.5V 3.5V 5.5V CC Supply Current (Low Noise Mode) 3.5V 5.5V CC Supply Current (Low Noise Mode) 3.5V 5.5V 3.5V 5.5V All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 8 MHz HALT mode VIN = 0V,VCC @ 2 MHz HALT mode VIN = 0V,VCC @ 2 MHz HALT mode VIN = 0V,VCC @ 8 MHz HALT mode VIN = 0V,VCC @ 8 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 4 MHz All Output and I/O Pins Floating @ 4 MHz 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 7 7 7 7 7 7 CP97DZ83501 PRELIMINARY 7 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA = 0C to +70C Sym Parameter ICC1 Standby Current (Low Noise Mode) VCC [4] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V ICC2 Standby Current 3.5V 5.5V IALL IALH Auto Latch Low Current Auto Latch High Current 3.5V 5.5V 3.5V 5.5V Min Max 1.2 1.6 1.5 1.9 2.0 2.4 10.0 10.0 12.0 32 -8.0 -16.0 Typical Note 4 @ 25C 0.4 0.9 0.5 1.0 0.8 0.3 1.0 1.0 3.0 16 -1.5 -8.0 Units mA mA mA mA mA mA A A A A A A Conditions HALT mode VIN = 0V,VCC @ 1 MHz HALT mode VIN = 0V,VCC @ 1 MHz HALT mode VIN = 0V,VCC @ 2 MHz HALT mode VIN = 0V,VCC @ 2 MHz HALT mode VIN = 0V,VCC @ 4 MHz HALT mode VIN = 0V,VCC @ 4 MHz STOP mode VIN = 0V, VCC WDT is not Running STOP mode VIN = 0V, VCC WDT is not Running 0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC Notes 7 7 7 7 7 7 7,8 7,8 6 6 6 6 Notes: 1. Port 2 and Port 0 only. 2. VSS = 0V = GND. 3. The device operates down to VRST of the specified frequency for VRST. The minimum operational VCC is determined on the value of the voltage VRST at the ambient temperature. The VRST increases as the temperature decreases. 4. VCC = 4.5V to 5.5V, typical values measured at VCC = 5.0V. 5. Standard Mode (not Low EMI mode). 6. Autolatches are enabled. 7. All outputs unloaded and all inputs are at VCC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level. 8 PRELIMINARY CP97DZ83501 Zilog TA = -40C to +105C Sym Parameter Max Input Voltage VCH Clock Input High Voltage VCC [4] 4.5V 5.5V 4.5V 5.5V VCL Clock Input Low Voltage 4.5V 5.5V VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V VOL1 Output Low Voltage 4.5V 5.5V 4.5V 5.5V VOL2 Output Low Voltage 4.5V 5.5V VOFFSET Comparator Input Offset Voltage VLV VCC Low Voltage Protection Input Leakage (Input Bias Current of Comparator) Output Leakage Comparator Input Common Mode Voltage Range Supply Current 4.5V 5.5V 4.5V 5.5V VVICR 4.5V 5.5V 2.3 Min Max 12.0 12.0 0.8 VCC VCC+0.3 0.8 VCC VCC+0.3 VSS-0.3 VSS-0.3 0.2 VCC 0.2 VCC 2.8 2.8 1.7 1.7 2.8 2.8 1.5 1.5 4.8 4.8 Typical Note 4 @ 25C Units V V V V V V V V V V V V V V 0.8 0.4 0.4 0.4 1.2 1.2 25.0 25.0 3.5 0.1 0.1 0.1 0.1 1.0 0.8 10.0 10.0 2.9 V V V V V V mV mV V Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Conditions IIN < 250 A IIN < 250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Notes 1 1 1 0.7 VCC VCC+0.3 0.7 VCC VCC+0.3 VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 0.2 VCC 0.2 VCC IOH = -2.0 mA IOH = -2.0 mA Low Noise @ IOH = -0.5 mA Low Noise @ IOH = -0.5 mA IOL = +4.0 mA IOL = +4.0 mA Low Noise @ IOL = 1.0 mA Low Noise @ IOL = 1.0 mA IOL = +10 mA, IOL = +10 mA, 5 5 5 5 5 5 @ 4 MHz Max. Int. CLK Freq. VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 3 IIL -1.0 -1.0 -1.0 -1.0 VSS -0.3 VCC -1.5 1.0 1.0 1.0 1.0 A A A A V IOL ICC 4.5V 5.5V 4.5V 5.5V 7.0 7.0 11.0 11.0 6.8 6.8 8.2 8.2 mA mA mA mA All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 8 MHz 5,7 5,7 5,7 5,7 CP97DZ83501 PRELIMINARY 9 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA = -40C to +105C Sym ICC1 Parameter Standby Current VCC [4] 4.5V 5.5V 4.5V 5.5V ICC Supply Current (Low Noise Mode) 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Min Max 3.0 3.0 5.0 5.0 7.0 7.0 9.0 9.0 11.0 11.0 Typical Note 4 @ 25C 2.5 2.5 3.0 3.0 6.8 6.8 7.5 7.5 8.2 8.2 Units mA mA mA mA mA mA mA mA mA mA Conditions HALT mode VIN = 0V, VCC @ 2 MHz HALT mode VIN = 0V, VCC @ 2 MHz HALT mode VIN = 0V, VCC @ 8 MHz HALT mode VIN = 0V, VCC @ 8 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 4 MHz All Output and I/O Pins Floating @ 4 MHz Notes 5,7 5,7 5,7 5,7 7 7 7 7 7 7 10 PRELIMINARY CP97DZ83501 Zilog TA = -40C to +105C Sym ICC1 Parameter Standby Current (Low Noise Mode) VCC [4] 4.5V 5.5V 4.5V 5.5V ICC2 Standby Current 4.5V 5.5V ALL Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Typical Note 4 @ 25C 0.9 0.9 1 1 1.0 1.0 16 16 -8.0 -8.0 Units mA mA mA mA A A A A A A Conditions HALT mode VIN = 0V, VCC @ 1 MHz HALT mode VIN = 0V, VCC @ 1 MHz HALT mode VIN = 0V, VCC @ 2 MHz HALT mode VIN = 0V, VCC @ 2 MHz STOP mode VIN = 0V, VCC WDT is not Running STOP mode VIN = 0V, VCC WDT is not Running 0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC Notes 7 7 7 7 7,8 7,8 6 6 6 6 Min Max 1.6 1.6 1.9 1.9 20 20 40 40 -20.0 -20.0 1 Auto Latch Low Current Auto Latch High Current 4.5V 5.5V 4.5V 5.5V IALH Notes: 1. Port 2 and Port 0 only. 2. VSS = 0V = GND. 3. The device operates down to VRST of the specified frequency for VRST. The minimum operational VCC is determined on the value of the voltage VRST at the ambient temperature. The VRST increases as the temperature decreases. 4. VCC = 4.5V to 5.5V, typical values measured at VCC = 5.0V. 5. Standard Mode (not Low EMI mode). 6. Autolatches are enabled. 7. All outputs unloaded and all inputs are at VCC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level. CP97DZ83501 PRELIMINARY 11 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog AC ELECTRICAL CHARACTERISTICS 1 3 Clock 2 7 7 2 3 T IN 4 6 5 IRQ N 8 9 Figure 6. AC Electrical Timing Diagram 12 PRELIMINARY CP97DZ83501 Zilog Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) TA= 0C to +70C 8 MHz No 1 2 3 4 5 6 7 8 9 10 11 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL TwIH Twdt Tpor Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Time Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Delay Time for Timeout Power-On Reset Time VCC 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min 125 125 Max DC DC 25 25 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 [ 1 1 1 1 [ 1 1 1,2 1,2 1 1,2 1 1 1 1 1 62 62 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 10 5 4 2 ns ns ns ns 36 18 ms ms ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). CP97DZ83501 PRELIMINARY 13 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) TA= -40C to +105C 8 MHz No 1 2 3 4 5 6 7 8 9 10 11 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL TwIH Twdt Tpor Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timer Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Delay Time for Timeout Power-On Reset Time VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Min 125 125 Max DC DC 25 25 62 62 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1 1 1 70 70 5TpC 5TpC 8TpC 8TpC 100 100 70 70 5TpC 5TpC 5 5 2 2 ns ns ns ns 20 20 ms ms ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 14 PRELIMINARY CP97DZ83501 Zilog Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller AC ELECTRICAL CHARACTERISTICS Low Noise Mode TA= 0C to +70C 1 MHz 4 MHz Min Max Min Max 1000 1000 DC DC 25 25 250 250 DC DC 25 25 1 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1 No 1 2 3 4. 5 6 7 8 9 10 Symbol TPC TrC TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL Low Time TwIH High Time Twdt Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timer Int. Request Input Int. Request Input Watch-Dog Timer Delay Time for Timeout VCC 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 500 500 100 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 100 70 2.5TpC 2.5TpC 10 5 125 125 100 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 100 70 2.5TpC 2.5TpC 10 5 ns ns ns ns ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). CP97DZ83501 PRELIMINARY 15 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog AC ELECTRICAL CHARACTERISTICS Low Noise Mode TA= -40C to +105C 1 MHz 4 MHz Min Max Min Max 1000 1000 DC DC 25 25 250 250 DC DC 25 25 No 1 2 3 4. 5 6 7 8 9 10 Symbol TPC TrC TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL TwIH Twdt Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timer Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Delay Time for Timeout VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1 500 500 70 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 70 70 2.5TpC 2.5TpC 5 5 125 125 70 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 70 70 2.5TpC 2.5TpC 5 5 ns ns ns ns ms ms Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 16 PRELIMINARY CP97DZ83501 Zilog Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller LOW NOISE VERSION Low EMI Emission The Z86E02 can be programmed to operate in a Low EMI emission mode by means of a mask ROM bit option. Use of this feature results in: s s s s Output drivers have resistances of 200 ohms (typical). Oscillator divide-by-two circuitry eliminated. 1 All pre-driver slew rates reduced to 10 ns typical. Internal SCLK/TCLK operation limited to a maximum of 4 MHz - 250 ns cycle time. The Low EMI mode is mask-programmable to be selected by the customer at the time the ROM code is submitted. (c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com CP97DZ83501 PRELIMINARY 17 Z86E02 SL1925 CMOS Z8(R) OTP Microcontroller Zilog 18 PRELIMINARY CP97DZ83501 |
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